1. Field of the Invention
The present invention relates to the field of asynchronous data transmissions and in particular to the asynchronous data transmission devices called “UARTs” (Universal Asynchronous Receiver Transceiver).
The present invention relates more particularly to a programmable clock generator to deliver, using a primary clock signal of determined frequency and period, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M.
2. Description of the Related Art
FIGS. 1 and 2 schematically show an example of data transmission between two UART circuits (UART1, UART2). Each UART circuit has a transmission terminal Tx connected to one receiving terminal Rx of the other UART circuit. The data transmission includes transmitting characters CHAR1, CHAR2 . . . each comprising 8 data bits B0 to B7 preceded by a start bit STB and followed by a stop bit SPB (FIG. 2).
Unlike synchronous data transmissions, the receiver (UART1 or UART2) does not receive the clock signal from the transmitter, such that each UART circuit has its own clock signal Hb to analyze the signal received and deduce the logic value of the bits carried by this signal from it. Therefore, the clock signal of the receiver must have a deviation that does not exceed a certain value in relation to that of the transmitter, so that the data can be properly received.
In order to increase the transfer possibilities of asynchronous data between devices having clock generators capable of having high drifts with time and temperature, data transmission protocols have been developed which enable the receiver to set its clock signal to that of the transmitter, by sending a synchronization character SYNC. This character SYNC, such as [55]h in hexadecimal notation for example, i.e., the character “10101010” in binary notation (bits B0 to B7), provides the receiver with several falling edges that enable it to match its clock signal to the reference clock signal carried by the character SYNC.
Changes in the baud rate may therefore be provided and a frequency reset of a UART circuit may occur at any time. However, the choice of the frequency of the local clock signal can only be made between two discrete values separated by a frequency step which is sometimes too high to provide satisfactory synchronization.
This problem will be better understood by referring to FIG. 3, which represents the classical architecture of a UART circuit data reception stage and a clock generator CKGEN1 that drives the data reception stage.
The circuit CKGEN1 comprises a programmable divider DIV1 receiving at a first input a primary clock signal Ho of frequency Fo and period To delivered by an oscillator OSC, and at a second input a set point M1. The set point M1 is a whole number generally coded on 8 bits, i.e., a whole number between 1 and 255 (the value 0 being unusable). The divider DIV1 delivers an oversampling clock signal Hs of frequency Fs=Fo/M1 and of period Ts=M1*To. The clock generator CKGEN1 also comprises a divider by N DIV2 receiving the signal Hs at input and delivering a bit clock signal Hb of frequency Fb=Hs/N, i.e., Fb=Ho/M1*N, and of period Tb=N*Ts, i.e., Tb=N*M1*To. The frequency of the bit clock signal Hb determines the baud rate.
The signal received on the terminal Rx of the UART circuit is applied to a shift register OSREG (“Oversampling Shift Register”) driven by the clock signal Hs. The register OSREG has a parallel output that is applied to the input of a circuit MBVC and to the input of a circuit STBDET. The circuit STBDET is a detector circuit of the start bit STB. The circuit MBVC is a majority calculation circuit that determines the majority value of K samples received during a cycle of N pulses of the oversampling clock signal Hs (i.e., a period of the signal Hb) as being the value of a received bit. Generally speaking, N is equal to 16 and K=3, such that 3 samples out of 16 are analyzed at each clock period Hb. They are the three middle samples of the series of N samples received, i.e., the 7th, 8th and 9th samples where N=16.
The bits B0, B1, . . . B7 of each character received are therefore delivered one by one by the circuit MBVC and applied to a shift register DTREG (“Data Register”) driven by the clock signal bit Hb. These operations are carried out under the control of a sequencer SEQ, generally a hard-wired logic state machine, which in particular controls the unloading of the registers OSREG and DTREG and receives a signal DET for detecting the start bit delivered by the circuit STBDET.
FIG. 4 shows an oversampling sequence of a bit Bn of rank n, in the event that M1=25 and N=16. 16 samples S0 to S15 are obtained the duration of which is equal to the period Ts of the pulses of the clock signal Hs, Ts here being equal to 25*To. The value of the bit Bn delivered by the circuit MBVC corresponds to the majority value of the samples S6, S7 and S8 (7th, 8th and 9th samples).
In summary, the set point M1 supplied to the generator CKGEN1 determines the frequency of the oversampling clock signal Fs and the frequency of the bit clock signal Hs. The set point M1 is delivered by a unit BDU for determining the baud rate (“Baud Rate Control Unit”) and is stored in a register BRREG (“Baud Rate Register) the output of which is applied to the generator CKGEN1. The unit BDU may be a hard-wired logic unit specialized in the analysis of the character SYNC described above or a programmable circuit such as a microprocessor.
As indicated above, the set point M1 may be modified at any time by the unit BDU. The difference ΔFs % between two adjacent oversampling frequencies Fs1, Fs2 (i.e., an increment of 1 applied to the set point M1) is equal to:
                                          (            1            )                    ⁢                                          ⁢          Δ          ⁢                                          ⁢          Fs          ⁢                                          ⁢          %                =                  100          *                                    (                                                F                  ⁢                                                                          ⁢                  s2                                -                Fs1                            )                        /            Fs1                                                            ⇒                                    (              2              )                        ⁢            Δ            ⁢                                                  ⁢            Fs            ⁢                                                  ⁢            %                          =                  100          *                                    [                                                (                                      Fo                    /                    M1                                    )                                -                                  (                                      Fo                    /                                          (                                              M1                        +                        1                                            )                                                        )                                            ]                        /                          (                              Fo                /                                  (                                      M1                    +                    1                                    )                                            )                                                                        ⇒                                    (              3              )                        ⁢            Δ            ⁢                                                  ⁢            Fs            ⁢                                                  ⁢            %                          =                  100          *                      [                                          (                                  M1                  +                                      1                    /                    M1                                                  )                            -              1                        ]                                                            ⇒                                    (              4              )                        ⁢            Δ            ⁢                                                  ⁢            Fs            ⁢                                                  ⁢            %                          =                  100          /          M1                    
When the analysis of the synchronization character leads the unit BDU to find a baud rate half-way between the two possible values Fs1, Fs2, the clock reset error or synchronization error SYNCERR(Fs) is equal to half the increment ΔFs %, i.e.:SYNCERR(Fs)=100/2M1%
It can be seen that the synchronization error SYNCERR(Fb) on the frequency of the bit clock signal Hb is identical to the error SYNCERR(Fs):
                                          (            5            )                    ⁢                                          ⁢          Δ          ⁢                                          ⁢          Fb          ⁢                                          ⁢          %                =                  100          *                                    [                                                (                                                            Fo                      /                      N                                        *                    M1                                    )                                -                                  (                                                            Fo                      /                      N                                        *                                          (                                              M1                        +                        1                                            )                                                        )                                            ]                        /                          (                                                Fo                  /                  N                                *                                  (                                      M1                    +                    1                                    )                                            )                                                                        ⇒                                    (              6              )                        ⁢            Δ            ⁢                                                  ⁢            Fb            ⁢                                                  ⁢            %                          =                  100          *                                    [                                                (                                      Fo                    /                    M1                                    )                                -                                  (                                      Fo                    /                                          (                                              M1                        +                        1                                            )                                                        )                                            ]                        /                          (                              Fo                /                                  (                                      M1                    +                    1                                    )                                            )                                                                        ⇒                                    (              7              )                        ⁢            Δ            ⁢                                                  ⁢            Fb            ⁢                                                  ⁢            %                          =                  Δ          ⁢                                          ⁢          Fs          ⁢                                          ⁢          %                                                  ⇒                                    (              8              )                        ⁢                                                  ⁢                          SYNCERR              ⁡                              (                Fb                )                                                    =                  SYNCERR          ⁡                      (            Fs            )                              
This error is even higher the lower the set point M1 is. For M1=25, for example, the synchronization error SYNCERR is around 2% when the frequency of the oversampling clock signal Fs is shifted onto the neighboring frequency Fo/(M1+1) or Fo/(M1−1). This error is much higher for values of M1 between 1 and 24. Yet, an error of 2% already represents the limit accepted by certain protocols such as the LIN protocol (Local Interconnect Network).
One solution to this problem may include increasing the frequency of the primary clock signal Fo. If the frequency Fo is doubled for example, the limit value of the set point M1 which enables the error threshold of 2% to be reached is divided by two (i.e., M1=12 or M=13). However, this increase in primary frequency is not desirable in practice.
Another solution may include using a voltage-controlled oscillator (VCO), driven by a phase locked loop (PLL). However, voltage-controlled oscillators are bulky and expensive, and UART circuits are products whose price must be low.